1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of adjusting etching to deposition ratio of epitaxial layer for lowering defect.
2. Description of the Prior Art
Reduction of the size and the inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of MOS devices, stress may be introduced in the channel region of a MOS transistor to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (“PMOS”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is growing epitaxial layer such as SiGe stressors in the source and drain regions. Such a method typically includes the steps of forming agate stack on a semiconductor substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate along gate spacers, epitaxially growing SiGe stressors in the recesses and annealing. Since SiGe has a greater lattice constant than silicon, it expands after annealing and applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor.
The above-discussed method, however, has found to include numerous defects especially after the formation of epitaxial layer. Hence, how to adjust the current fabrication flow for resolving this issue has become an important task in this field.